Date Available
4-17-2013
Year of Publication
2013
Document Type
Master's Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
College
Engineering
Department/School/Program
Electrical Engineering
Advisor
Dr. Henry Dietz
Abstract
Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.
Recommended Citation
Sparks, Matthew A., "A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTURE" (2013). Theses and Dissertations--Electrical and Computer Engineering. 26.
https://uknowledge.uky.edu/ece_etds/26
