Date Available
4-28-2013
Year of Publication
2013
Document Type
Master's Thesis
Degree Name
Master of Electrical Engineering (MEE)
College
Engineering
Department/School/Program
Electrical Engineering
Advisor
Dr. Meikang Qiu
Abstract
The gradually widening speed disparity of between CPU and memory has become an overwhelming bottleneck for the development of Chip Multiprocessor (CMP) systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this thesis focuses on proposing a new heterogeneous scratchpad memory architecture which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms, a dynamic programming and a genetic algorithm, to perform data allocation to different memory units, therefore reducing memory access cost in terms of power consumption and latency. Extensive and intensive experiments are performed to show the merits of the heterogeneous scratchpad architecture over the traditional pure memory system and the effectiveness of the proposed algorithms.
Recommended Citation
Chen, Zhi, "Power-Efficient and Low-Latency Memory Access for CMP Systems with Heterogeneous Scratchpad On-Chip Memory" (2013). Theses and Dissertations--Electrical and Computer Engineering. 25.
https://uknowledge.uky.edu/ece_etds/25
