Author ORCID Identifier
https://orcid.org/0009-0001-7701-051X
Date Available
12-3-2025
Year of Publication
2024
Document Type
Master's Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
College
Engineering
Department/School/Program
Electrical Engineering
Advisor
Dr. Daniel Lau
Abstract
Digital halftoning reproduces continuous-tone images using patterns of black and white dots, while multitoning extends this concept by incorporating inks with intermediate intensities. These techniques are extensively utilized in the printing industry to accommodate the limited range of inks available in printers. Stacked error diffusion is a high-quality multitoning algorithm that adheres to the blue-noise dithering standard. This thesis research studies the potential parallelism inherent in the algorithm and introduces the design of a novel processor architecture optimized for efficient execution. The architecture is realized on an FPGA development board featuring a Zynq SoC. Additionally, the hardware prototype can also run a software implementation of the algorithm, leveraging the ARM CPU within the SoC. Test results confirmed both the functional correctness of the processor architecture and its substantial acceleration capability.
Digital Object Identifier (DOI)
https://doi.org/10.13023/etd.2024.426
Recommended Citation
Hu, Qishi, "A NOVEL PROCESSOR ARCHITECTURE IMPLEMENTING THE STACKED ERROR DIFFUSION ALGORITHM AND ITS ZYNQ-BASED REALIZATION" (2024). Theses and Dissertations--Electrical and Computer Engineering. 206.
https://uknowledge.uky.edu/ece_etds/206
Included in
Computer and Systems Architecture Commons, Digital Circuits Commons, Electrical and Electronics Commons, Hardware Systems Commons, Signal Processing Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
