Date Available

1-2-2023

Year of Publication

2022

Document Type

Doctoral Dissertation

Degree Name

Doctor of Philosophy (PhD)

College

Engineering

Department/School/Program

Electrical and Computer Engineering

Advisor

Dr. Himanshu Thapliyal

Co-Director of Graduate Studies

Dr. Michael T. Johnson

Abstract

Internet of Things (IoT) is a collection of devices that exchange data through a network to implement complex applications. IoT devices increase the quality of life of their user base which has a wide variety such as the medical field, consumer electronics, and the manufacturing sector. However, IoT devices have several challenges that need to be overcome namely, security and energy consumption. The threat vector that IoT devices face is growing and includes the following threats, the leakage of information through a side-channel attack known as the Correlation Power Analysis (CPA), authentication, piracy, etc. A side-channel attack is an attack that attempts to steal a device’s information through uncontrollable device side-channels such as timing, power consumption, electromagnetic radiation, etc. CPA is a type of side-channel attack that exploits variation in the power consumption within a device to steal an encryption key. There are many countermeasures to CPA attacks, however, many of these countermeasures consume substantial energy which makes them non-ideal for IoT devices which are typically battery operated. Thus, it is important to research and develop countermeasures to CPA attacks that consume minimal amounts of energy. In this thesis, we have explored the use of a novel, low-energy design technique known as adiabatic logic and an emerging memory technology known as Magnetic Tunnel Junctions (MTJ) to design ultra-low-energy and CPA resistant circuits for use in IoT devices. Furthermore, we have also researched the use of adiabatic logic and MTJs in designing a security primitive known as Physically Unclonable Functions (PUF) that can be helpful against attacks on privacy, authentication, and secure key generation. Adiabatic logic is an ultra-low energy circuit design technique that utilizes power clocks to supply and recover charge from a circuit. Adiabatic logic reduces the dynamic energy consumption of a circuit by recycling unused charge in the load capacitor back into the circuit to be reused again. Adiabatic logic is typically constructed using a 4-phase power clock however, the area and complexity of the power clock generator is a design limitation. Thus, the first contribution of this thesis is the conversion of an existing adiabatic logic

family known as Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) into a functional and energy-efficient two-phase implementation. 2-EE-SPFAL has less complex routing and less complex power clock design when compared to EE-SPFAL and is energy-efficient compared to standard CMOS. Furthermore, 2-EE-SPFAL has uniform power consumption regardless of data transition and thus is shown to be secure against power analysis attacks. Adiabatic logic reduces the dynamic energy consumption of a circuit but as the technology node decreases through sub 45nm the leakage power of an integrated circuit becomes a limiting factor. To that end, the second contribution of this thesis is the design of a hybrid adiabatic and MTJ circuit architecture. One of the main advantages of MTJs is the near-zero leakage power they consume which is essential as technology nodes scale down. To create an ultra-low energy circuit, we combine the dynamic energy savings of adiabatic logic with the leakage power savings of MTJs to create Energy- Efficient Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is energyefficient when compared with standard CMOS circuits as well as CMOS/MTJ circuits. We also show that EE-ACML is CPA resistant by implementing a lightweight cryptographic cipher called PRESENT utilizing EE-ACML and unsuccessfully stealing the encryption keys when performing a CPA attack. Authentication, privacy, and secure key generation are important considerations when designing IoT devices. One security primitive that can aid in solving the aforementioned issues is the Physically Unclonable Function (PUF). PUFs are security primitives that utilize manufacturing variation to give a device a unique digital fingerprint. The third contribution of this thesis is the design of a hybrid adiabatic/MTJ PUF. The proposed PUF saves energy by utilizing the energy recovery of adiabatic logic as well as the reduced leakage power with the implementation of the MTJs. The source of manufacturing variation within the proposed PUF is dominated by the variation of the MTJs. The proposed adiabatic/MTJ PUF has lower energy consumption than many state-of-the-art PUFs proposed in the literature. The clock generator of an adiabatic circuit is an essential component of any adiabatic system. Adiabatic clock generators come in many forms based on the number of phases they produce. For example, a 2-phase clock generator can produce a 2-phase clock in the form of a sinusoidal waveform. Different adiabatic circuits are constructed using these different clock generators and are shown to be energy-efficient. However, there is a lack of comparison on clock generators in terms of both energy efficiency and security against power analysis attacks. Thus, we perform a comparative study on 2 and 4-phase clock generators to analyze the trade-offs between energy efficiency and security of adiabatic clock generators.

Digital Object Identifier (DOI)

https://doi.org/10.13023/etd.2022.263

Funding Information

This work was supported by the National Science Foundation CAREER Award No. 1845448 and the Department of Education’s GAANN Fellowship Program through the University of Kentucky Electrical and Computer Engineering Department

Download

Share

COinS