Year of Publication

2020

Degree Name

Master of Science in Electrical Engineering (MSEE)

Document Type

Master's Thesis

College

Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Vijay P. Singh

Abstract

Nanostructured CdS/Cu2S devices have been simulated using SCAPS-1D to demonstrate enhanced performance over traditional planar device structures. Two designs were examined: a nanowire CdS/planar Cu2S device and a nanowire CdS/nanowire Cu2S device. The addition of nanowires to a device had been previously demonstrated to improve device performance in a nanowire CdS/planar CdTe device by decreasing the amount of light absorbed by the CdS window layer, thus allowing more light to reach the absorber layer. Additionally, the total number of interface states can be greatly reduced due to the decreased total surface area between the window and absorber layers. The nanowire CdS/planar Cu2S device showed an increase in efficiency of 0.88% over an optimized planar device. The nanowire CdS/nanowire Cu2S device showed an increase in efficiency of 1.16% over the optimized planar device. This shows that there is a significant benefit to the addition of nanostructures to CdS/Cu2S solar cell devices.

Digital Object Identifier (DOI)

https://doi.org/10.13023/etd.2020.166

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