Date Available
4-29-2019
Year of Publication
2019
Document Type
Master's Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
College
Engineering
Department/School/Program
Electrical and Computer Engineering
Advisor
Dr. Henry G. Dietz
Abstract
LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.
Digital Object Identifier (DOI)
https://doi.org/10.13023/etd.2019.141
Recommended Citation
Eberhart, Paul S., "A Compiler Target Model for Line Associative Registers" (2019). Theses and Dissertations--Electrical and Computer Engineering. 138.
https://uknowledge.uky.edu/ece_etds/138
