Year of Publication

2019

Degree Name

Master of Science in Electrical Engineering (MSEE)

Document Type

Master's Thesis

College

Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Henry G. Dietz

Abstract

LARs (Line Associative Registers) are very wide tagged registers, used for both register-wide SWAR (SIMD Within a Register )operations and scalar operations on arbitrary fields. LARs include a large data field, type tags, source addresses, and a dirty bit, which allow them to not only replace both caches and registers in the conventional memory hierarchy, but improve on both their functions. This thesis details a LAR-based architecture, and describes the design of a compiler which can generate code for a LAR-based design. In particular, type conversion, alignment, and register allocation are discussed in detail.

Digital Object Identifier (DOI)

https://doi.org/10.13023/etd.2019.141

Share

COinS