Year of Publication


Degree Name

Master of Science in Electrical Engineering (MSEE)

Document Type





Electrical Engineering

First Advisor

Dr. Vijay P Singh


This work focuses on the growth of vertically aligned CdTe nanowire arrays of controllable diameter and length using cathodic electro deposition in anodized alumina templates. This step was followed by annealing at 250° C in a reducing environment (95% Ar + 5% H2). AAO template over ITO-glass was used as starting template for the device fabrication. The deposited nanowires showed nanocrystalline cubic phase structures with a strong preference in [111] direction. First gold (Au) was deposited into AAO using cathodic electro deposition. This was followed by CdTe deposition into the pore. Gold was deposited first as it aids the growth of CdTe inside AAO and it makes Schottky contact with the deposited n type CdTe. CdTe was determined to be n-type from the fact that back to back diode was obtained with Au-CdTe-Au test structure. Aluminum (Al) was sputtered on the top to make the ohmic contact to the n type CdTe deposited in AAO. Analysis of Schottky diodes yielded a diode ideality factor of 10.03 under dark and 10.08 under light and reverse saturation current density of 34.9μA/cm2 under dark and 39.7μA/cm2 under light.