Date Available


Year of Publication


Document Type





Electrical Engineering

First Advisor

Arthur V. Radun


This thesis develops a hardware circuit implementation of a novel algorithm for reducing a SRM drives input current ripple or equivalently to improve the SRM drives input power quality. The algorithm requires the SRMs phase current to follow a trapezoidal trajectory relative to the rotors position with the magnitude of the current dependent on the desired average torque. This thesis deals with the generation of the required current command that is the input to a separate analog current regulator that forces the SRMs current to follow the generated current command. The final circuit design must be capable of operating at 200C to be part of a high temperature aircraft actuator. In this thesis, room temperature hardware is used to emulate and verify the high temperature design. Both a high temperature microcontroller based design and a high temperature gate array based design are considered with the high temperature gate array based design being chosen. Ultimately, a standard room temperature Xilinx FPGA is chosen to emulate the high temperature gate array. The FPGA is programmed using Verilog HDL and the code is downloaded into the chip using Xilinx ISE software. The experimentally generated output is validated by comparing it with simulation results from a detailed Simulink model of the complete drive system.