Year of Publication

2015

Degree Name

Master of Science in Electrical Engineering (MSEE)

Document Type

Master's Thesis

College

Engineering

Department

Electrical and Computer Engineering

First Advisor

Dr. Himanshu Thapliyal

Abstract

This thesis is based on promising computing paradigm of reversible logic which generates unique outputs out of the inputs and. Reversible logic circuits maintain one-to-one mapping inside of the inputs and the outputs. Compared to the traditional irreversible computation, reversible logic circuit has the advantage that it successfully avoids the information loss during computations. Also, reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and the nanocircuits that are testable in nature. Reversible computing circuits require the ancilla inputs and the garbage outputs. Ancilla input is the constant input in reversible circuits. Garbage output is the output for maintaining the reversibility of the reversible logic but is not any of the primary inputs nor a useful bit. An efficient reversible circuit will have the minimal number of garbage and ancilla bits.

Barrel shifter is one of main computing systems having applications in high speed digital signal processing, oating-point arithmetic, FPGA, and Center Processing Unit (CPU). It can operate the function of shifting or rotation for multiple bits in only one clock cycle. The goal of this thesis is to design barrel shifters based on the reversible computing that are optimized in terms of the number of ancilla and garbage bits. In order to achieve this goal, a new Super Conservative Reversible Logic Gate (SCRL gate) has been used. The SCRL gate has 1 control input depending on the value of which it can swap any two n-1 data inputs. We proved that the SCRL gate is superior to the existing conservative reversible Fredkin gate. This thesis develops 5 design methodologies for reversible barrel shifters using SCRL gates that are primarily optimized with the criteria of the number of ancilla and garbage bits. The five proposed methodologies consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter and reversible universal bidirectional shifter. The proposed reversible barrel shifter design is compared with the existing works in literature and have shown improvement ranging from 8.5% to 92% by the number of garbage and ancilla bits. The SCRL gate and design methodologies of reversible barrel shifter are mapped in Quantum Dot Cellular Automata (QCA) computing. It is illustrated that the SCRL-based designs of reversible barrel shifters have less QCA cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate- based designs of reversible barrel shifters.

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