Date Available
4-19-2011
Year of Publication
2010
Document Type
Thesis
Degree Name
Master of Science in Electrical Engineering (MSEE)
College
Engineering
Department
Electrical Engineering
Advisor
Dr. J. Robert Heath
Co-Director of Graduate Studies
Dr. Daniel Lau
Abstract
Digital halftoning is a crucial technique used in digital printers to convert a continuoustone image into a pattern of black and white dots. Halftoning is used since printers have a limited availability of inks and cannot reproduce all the color intensities in a continuous image. Error Diffusion is an algorithm in halftoning that iteratively quantizes pixels in a neighborhood dependent fashion. This thesis focuses on the development and design of a parallel scalable hardware architecture for high performance implementation of a high quality Stacked Error Diffusion algorithm. The algorithm is described in ‘C’ and requires a significant processing time when implemented on a conventional CPU. Thus, a new hardware processor architecture is developed to implement the algorithm and is implemented to and tested on a Xilinx Virtex 5 FPGA chip. There is an extraordinary decrease in the run time of the algorithm when run on the newly proposed parallel architecture implemented to FPGA technology compared to execution on a single CPU. The new parallel architecture is described using the Verilog Hardware Description Language. Post-synthesis and post-implementation, performance based Hardware Description Language (HDL), simulation validation of the new parallel architecture is achieved via use of the ModelSim CAD simulation tool.
Recommended Citation
Kora Venugopal, Rishvanth, "FPGA BASED PARALLEL IMPLEMENTATION OF STACKED ERROR DIFFUSION ALGORITHM" (2010). University of Kentucky Master's Theses. 40.
https://uknowledge.uky.edu/gradschool_theses/40
