Year of Publication

2011

Degree Name

Master of Science in Electrical and Computer Engineering (MSECE)

Document Type

Thesis

College

Engineering

Department

Electrical Engineering

First Advisor

Dr. Vijay P. Singh

Abstract

This work focuses on a simple template assisted approach for fabricating I-III-VI semiconductor nanowire arrays. Vertically aligned nanowires of p-CIS of controllable diameter and thickness are electrodeposited, from an acidic electrolyte solution, inside porous aluminum templates using a three electrode set up with saturated calomel electrode as the reference. AAO template over ITO-glass was used as starting template for the device fabrication. The deposited CIS is annealed at different temperatures in a reducing environment (95% Ar+ 5% H2) for 30 minutes. X-ray diffraction of the nanowires showed nanocrystalline cubic phase structures with a strong orientation in the <112> direction. The effective bandgap of the deposited CIS nanowires determined using the Near Infrared (NIR) Spectrometer was found to be 1.07eV. The type of CIS electrodeposited inside the porous alumina template is determined to be p-type from the Schottky diode obtained with ITO-CIS-Au structure. Schottky diodes were characterized and analyzed at room temperature.

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