US Patent Number
A method of fault tolerant reconfiguration and operation of a field programmable gate array (FPGA) during normal on-line operation includes selecting a programmable logic block as a programmable logic block under test, testing the programmable logic block under test, and detecting the existence of any faults in the programmable logic block under test. During testing, the programmable logic block under test is repeatedly reconfigured in order to test the programmable logic block completely in all possible modes of operation. Based on the results of the test, a test result indication is sent to a controller in communication with a memory for storing usage and fault status data for each programmable logic block. If a partially faulty test result indication is present, the controller determines an intended mode of operation of the partially faulty programmable logic block under test and reconfigures the logic block for further use, thus allowing a more gradual degradation of the field programmable gate array.
Agere Systems Guardian Corp., Allentown, PA (US); University of Kentucky Research Foundation, Lexington, KY (US)
Abramovici, Miron and Stroud, Charles E., "Fault Tolerant Operation of Field Programmable Gate Arrays" (2001). Electrical and Computer Engineering Faculty Patents. 8.