US Patent Number
Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.
University of Kentucky Research Foundation, Lexington, Ky., Lucent Technologies Inc., Murray Hill, N.J.
Wu, Shianling; Karri, Ramesh; and Stroud, Charles Eugene, "Maintenance Registers with Boundary Scan Interface" (2000). Electrical and Computer Engineering Faculty Patents. 12.